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| regarding the change of names mentioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: http://www.renesas.com renesas technology corp. customer support dept. april 1, 2003 to all our customers
cautions keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or an y other rights, belonging to renesas technology corporation or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained i n these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, an d algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lice nse from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein. hitachi microcomputer technical q & a h8/300h series application notes hitachi micro systems, incorporated 1994 ade-502-038 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachi? permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user? unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachi? semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachi? products are not authorized for use in medical appli- cations without the written consent of the appropriate officer of hitachi? sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachi? prod- ucts are requested to notify the relevant hitachi sales offices when planning to use the prod- ucts in medical applications. introduction the h8/300h series microcontrollers are high-performance hitachi-original 16-bit microcontrollers that build in the optimum peripheral equipment for industrial machinery around high-speed h8/300 cpus that have architecture upwardly compatible with h8/300 cpus. the microcontroller puts a cpu, ram, direct memory access controller (dmac), bus controller, timers, and a serial communication interface (sci) on a single chip, making it suitable for a wide range of applications from small to large systems. this microcontroller technical q&a covers the h8/3001, h8/3002, h8/3003, h8/3042 series, h8/3032 series, and h8/3048 series. table 0-1 h8/300h series item h8/3003 h8/3002 h8/3001 h8/3042 h8/3041 h8/3040 cpu h8/300h h8/300h h8/300h h8/300h h8/300h h8/300h memory rom mask (byte) 64 k 48 k 32 k ztat ? *?es ram (byte) 512 512 512 2 k 2 k 2 k address space (byte) 16 m 16 m 16 m 16 m 16 m 16 m external data bus width (bit) 8/16 8/16 8/16 8/16 8/16 8/16 timers itu (integrated 5 ch 5 ch 5 ch 5 ch 5 ch 5 ch timer unit) watchdog timer 1 ch 1 ch 1 ch 1 ch 1 ch dma memory ? i/o 8 ch 4 ch 4 ch 4 ch 4 ch controller memory ? memory 4 ch 2 ch 2 ch 2 ch 2 ch programmable timing pattern 16 bits 16 bits 12 bits 16 bits 16 bits 16 bits controller (tpc) sci (asynchronous/clock- 2 ch 2 ch 1 ch 2 ch 2 ch 2 ch synchronous) a/d resolution 10 bits 10 bits 10 bits 10 bits 10 bits 10 bits converter input channel 8 ch 8 ch 4 ch 8 ch 8 ch 8 ch external trigger input yes yes yes yes yes yes d/a resolution ? bits 8 bits 8 bits converter input channel ? ch2 ch2 ch refresh controller on-chip on-chip on-chip on-chip on-chip interrupts external interrupts 974777 internal interrupts 34 30 20 30 30 30 i/o port 58 46 32 78 78 78 package qfp-112 qfp-100 qfp-80 qfp-100 qfp-100 qfp-100 tqfp-100 tqfp-80 tqfp-100 tqfp-100 tqfp-100 miscellaneous note: ztat (zero turn around time) is a trademark of hitachi ltd. table i-1 h8/300h series (cont) item h8/3048 h8/3047 h8/3044 h8/3032 h8/3031 h8/3030 cpu h8/300h h8/300h h8/300h h8/300h h8/300h h8/300h memory rom mask (byte) 128 k 96 k 32 k 64 k 32 k 16 k ztat ? *yesyes ram (byte) 4 k 4 k 2 k 2 k 1 k 512 address space (byte) 16 m 16 m 16 m 1 m 1 m 1 m external data bus width (bit) 8/16 8/16 8/16 8 8 8 timers itu (integrated 5 ch 5 ch 5 ch 5 ch 5 ch 5 ch timer unit) watchdog timer 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch dma memory ? i/o 4 ch 4 ch 4 ch controller memory ? memory 2 ch 2 ch 2 ch programmable timing pattern 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits controller (tpc) sci (asynchronous/clock- 2 ch 2 ch 2 ch 1 ch 1 ch 1 ch synchronous) a/d resolution 10 bits 10 bits 10 bits 10 bits 10 bits 10 bits converter input channel 8 ch 8 ch 8 ch 8 ch 8 ch 8 ch external trigger input yes yes yes yes yes yes d/a resolution 8 bits 8 bits 8 bits converter input channel 2 ch 2 ch 2 ch refresh controller on-chip on-chip on-chip interrupts external interrupts 777666 internal interrupts 30 30 30 21 21 21 i/o port 78 78 78 63 63 63 package qfp-100 qfp-100 qfp-100 qfp-80 qfp-80 qfp-80 tqfp-100 tqfp-100 tqfp-100 tqfp-80 tqfp-80 tqfp-80 miscellaneous built-in smart card interface, improved low-voltage, low-power performance for users of the microcontroller technical q & a this microcontroller technical q & a was compiled from answers to technical questions we received from hitachi microcontroller users. we hope that it will be a useful addition to the h8/300h series user manuals . before starting design of products that use microcontrollers, read through the manual to deepen your understanding of microcontroller products and re-familiarize yourself with those areas of difficulty at the design stage. contents q&a no. page section 1 cpu registers (1) the difference between the ccr s v flag and c flag qa300h-001a 1 (2) the relationship between data size and v flag changes qa300h-002a 2 (3) use of general registers qa300h-003a 3 bus controller (1) bus state while the cpu is operating qa300h-004 4 (2) bus modes qa300h-005a 5 (3) setting the bus controller in area 7 qa300h-006a 6 (4) external installation of ram to 8-bit bus areas qa300h-007a 7 (5) changing the number of wait states inserted per area qa300h-008a 8 (6) receiving breq in power-down mode qa300h-009a 10 (7) maximum wait time after breq input qa300h-010a 11 interrupts (1) interrupt sampling qa300h-011a 12 (2) holding external interrupts qa300h-012a 13 (3) receiving nmis during nmi processing qa300h-013a 14 (4) edge rise and fall times for interrupt pins qa300h-014a 15 (5) disable timing for interrupts qa300h-015a 16 (6) exception processing after a reset qa300h-016a 17 (7) using the interrupt controller qa300h-017a 18 (8) receiving an external irq1 after returning from qa300h-018a 20 hardware standby mode (9) interrupt priority within groups qa300h-019a 21 (10) interrupts when the bus is released qa300h-020a 22 resets (1) nmi sampling timing and receiving after reset qa300h-021a 23 (2) initializing sp after reset qa300h-022a 24 (3) pin state during power-on reset qa300h-023a 25 (4) reso pin output from res pin input qa300h-024a 26 (5) connecting res and reso pins qa300h-025a 27 (6) cautions for reset input qa300h-026a 28 power-down mode (1) executing instructions when switching to hardware standby mode qa300h-027a 29 (2) mode pins during hardware standby mode qa300h-028a 30 (3) returning from hardware standby mode qa300h-029a 31 (4) interrupt sampling and receiving in sleep mode qa300h-030a 32 (5) execution time in software standby mode qa300h-031a 33 (6) operation when an interrupt is requested during execution or qa300h-032a 34 while fetching a sleep instruction q&a no. page instructions (1) support for the daa (das) instruction with the inc qa300h-033a 36 (dec) instruction (2) bra and brn instructions qa300h-034a 37 (3) brn instruction qa300h-035a 38 (4) the subx instruction qa300h-036a 39 (5) odd address values during stc instruction execution qa300h-037a 40 (6) interrupts and dma transfer requests while the eepmov qa300h-038a 41 instruction is executing (7) the difference between eepmov.b and eepmov.w qa300h-039a 42 miscellaneous (1) cautions on stack operation qa300h-040a 43 (2) on-chip peripheral lsi access when the bus is released qa300h-041a 44 (3) areas that can be used as rom by the vector table qa300h-042a 45 (4) pin state during the oscillation settling time qa300h-043a 46 section 2 on-chip peripherals dma controller (1) receiving dmac startup requests qa300h-101 47 (2) addresses during dma transfers qa300h-102 49 (3) tend signal output timing 1 qa300h-103 50 (4) tend signal output timing 2 qa300h-104 51 (5) the relationship between the dmac s dte and dtie bits qa300h-105 52 (6) dmac startup qa300h-106 53 (7) the dmac and timer interrupts qa300h-107 54 (8) operation after a dmac end interrupt is generated 1 qa300h-108 55 (9) operation after a dmac end interrupt is generated 2 qa300h-109 56 (10) dma transfers started up by serial transfers qa300h-110 57 (11) time until dmac startup by the dreq pin qa300h-111 58 (12) reverse operation in the dma repeat mode qa300h-112 59 (13) use of dual-function pins qa300h-113 60 (14) i/o ports and the dreq pin qa300h-114 61 itu (1) pwm mode and interrupts qa300h-115 62 (2) clearing the counters qa300h-116 63 (3) pulse output from the itu qa300h-117 64 (4) itu cascade connections qa300h-118 65 (5) setting the itu s pwm output qa300h-119 66 (6) itu output and port output qa300h-120 67 (7) itu settings qa300h-121 69 (8) independent operation of tcnt4 using reset-synchronized qa300h-122 72 pwm mode watchdog timer (1) halting the wdt s system clock qa300h-123 73 q&a no. page serial communications interface (sci) (1) using the rdr and tdr when the sci is not being used qa300h-124 74 (2) i/o settings of clock pins for the sci qa300h-125 75 (3) serial i/o pin state qa300h-126 76 (4) simultaneous transmission and reception with the sci qa300h-127 77 (5) rdrf qa300h-128 78 (6) setting for asynchronous transmission qa300h-129 79 (7) how data is transferred to the tdr qa300h-130 81 (8) timing of setting rdrf qa300h-131a 83 (9) timing of setting tdre qa300h-132a 85 (10) sci reception errors qa300h-133 87 (11) operating the sci in external clock mode qa300h-134 88 (12) system clocks and sck phases qa300h-135 89 a/d converter (1) changing the a/d mode and channel during a/d conversion qa300h-136 90 i/o ports (1) using general-purpose ports qa300h-137 91 (2) processing ports when not in use qa300h-138 92 1 classification?8/300h software o registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question answer product h8/300h q&a no. qa300h-001a topic the difference between the ccr s v flag and c flag since the ccr s v flag and c flag both flag a 1 when an operation overflows, what is the difference? the ccr s v flag is accessed to see if an overflow has occurred in a signed operation. in figure 1.1, which is a byte-sized operation, the flag is set to 1 when the result is smaller than the negative minimum (h'80) or larger than the positive maximum (h'7f). figure 1.1 v flag operation in contrast, the ccr s c flag is accessed to see if an overflow has occurred in an unsigned operation. in figure 1.2, which is a byte-sized operation, the flag is set to 1 when the result is smaller than the minimum (h'00) or larger than the maximum (h'ff). figure 1.2 c flag operation h'80 h'00 h'7f overflow v flag overflow h'00 h'ff overflow c flag overflow technical questions and answers section 1 cpu references 2 classification?8/300h software o registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product h8/300h q&a no. qa300h-002a topic the relationship between data size and v flag changes do the changes in the ccr s v flag vary with data size? the ccr s v flag changes when an overflow is detected in the result of a signed arithmetic operation. this operation is the same for all data sizes. however, the timing of the changes in the flag varies as follows: byte: when the value is smaller than h'80 or larger than h'7f. word: when the value is smaller than h'8000 or larger than h'7fff. longword: when the value is smaller than h'80000000 or larger than h'7fffffff. technical questions and answers 3 classification?8/300h software o registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title see section 2.4.2, general registers, in the following manuals: h8/3002 hardware manual h8/3003 hardware manual h8/3042 series hardware manual question references answer product h8/300h q&a no. qa300h-003a topic use of general registers can different general registers be used as 8-bit, 16-bit, and 32-bit registers at the same time? yes. registers can be set freely for use as shown in figure 1.3. figure 1.3 use of general registers e0 r0h e2 e4 e5 e6 er7 (sp) note: er7 is used as the sp without any special notice being given. er3 er1 r0l r2h r2l r6h e5 e4 r6l technical questions and answers 4 classification?8/300h software registers o bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title see figure 6.18, external bus release state, in the following manuals: h8/3002 hardware manual h8/3003 hardware manual h8/3042 series hardware manual question references answer product h8/300h q&a no. qa300h-004 topic bus state while the cpu is operating 1. what is the bus state during cpu internal processing? 2. what is the bus state after dreq is received? 3. what is the bus state after breq is received? see table 1.1. table 1.1 bus state while the cpu is operating cpu operation address bus data bus during internal cpu processing hold high impedance after dreq is received dma address dma data after breq is received high impedance high impedance technical questions and answers 5 classification?8/300h software registers o bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title see table 6.4, address space and data bus used, in the following manuals: h8/3002 hardware manual h8/3003 hardware manual h8/3042 series hardware manual question references answer product h8/300h q&a no. qa300h-005a topic bus modes section 6.2.1 of the h8/3003 hardware manual says, ?hen even 1 bit of the abwcr is cleared to 0, the bus mode becomes 16 bits.?does this mean that all areas can be accessed in 16-bit mode? no. when a given bit adwn (bus width control for area n) of the abwcr (bus width control register) is cleared to 0, only that area whose bit is cleared can be accessed in 16-bit mode. the manual description might better read, "when even one area is set as a 16-bit accessed space, the h8/300h cpu goes into 16-bit bus mode and d15?0 can all be used as the data bus. this means that i/o ports that are also used as the lower data bus (d7?0) cannot be used as general ports, even in an 8-bit access space." technical questions and answers 6 classification?8/300h software registers o bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title see figure 6.2, access area map for each operating mode, in the following manuals: h8/3002 hardware manual h8/3003 hardware manual h8/3042 series hardware manual question references answer product h8/300h q&a no. qa300h-006a topic setting the bus controller in area 7 when the rame (ram enable) bit of the syscr (system control register) is cleared to 0, the on-chip ram is not valid and the settings of area 7 are followed. the cs signal outputs low in all of area 7. since area 7 mixes on-chip ram and internal i/o registers, in which areas are the bus widths and access states set by the bus controller valid? in area 7, the bus width and number of access states set by the bus controller are valid in areas other than the on-chip ram and internal i/o registers. (the addresses of the area differ according to the product. see the manual for details.) on-chip ram has a fixed bus width of 16-bits and a fixed number of access states of 2. the internal i/o registers can have bus widths of 8-bits or 16-bits, and have a fixed number of access states of 3. technical questions and answers 7 classification?8/300h software registers o bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title see table 6.4, address space and data bus used, in the following manuals: h8/3002 hardware manual h8/3003 hardware manual h8/3042 series hardware manual question references answer product h8/300h q&a no. qa300h-007a topic external installation of ram to 8-bit bus areas when ram is externally installed in 8-bit bus space, which signal should be used to access it, hwr or lwr ? use the hwr signal. technical questions and answers 8 classification?8/300h software registers o bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title see section 6.3.5 (5), wsc setting example, in the following manuals: h8/3002 hardware manual h8/3003 hardware manual h8/3042 series hardware manual question answer product h8/300h q&a no. qa300h-008a-1 topic changing the number of wait states inserted per area 1. can the wait mode be set for individual areas? 2. if not, how should the wait mode be set to change the number of access states inserted for individual areas? 1. wms (wait mode select) bits 1 and 0 of the wcr (wait control register), which set the wait mode, are common to all areas. for this reason, the wait mode cannot be set for individual areas. 2. the following areas, can, however, be mixed: wait disabled areas areas to which wait states are only inserted by the wait pin (pin wait mode 0) areas in which wc (wait count) bits 1 and 0 of the wcr are valid (programmable wait mode, pin wait mode 1, or pin auto- wait mode) the number of access states for individual areas can be changed by using these in combination. an example is shown below and in tables 1.2 and 1.3. technical questions and answers references the bus width and the enabled/disabled state of wsc (wait state controller) operation can be set for individual areas. 9 answer product h8/300h q&a no. qa300h-008a-2 topic changing the number of wait states inserted per area example: to set the following access states for the following areas: areas 0?: 2 states area 2: 3 states areas 3?: 4 states area 5: 5 states areas 6?: 6 states table 1.2 changing the number of wait states inserted per area wait states enable/disable of wait waits from access area memory map from wc bit insertion from wait pin wait pin states area 0 2-state access space invalid disable 2 area 1 wait-disabled area area 2 3-state access space invalid enable 0 3 pin wait mode 0 area 3 valid/1 state enable 0 4 area 4 3-state access space pin wait mode 1 area 5 enable 1 5 area 6 3-state access space invalid enable 3 6 area 7 pin wait mode 0 table 1.3 register settings register address setting 70 astcr (access state control register) h'fc 11111100 70 wcer (wait state control enable register) h'38 00111000 70 wcr h'f9 1001 technical questions and answers 10 classification?8/300h software registers o bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product h8/300h q&a no. qa300h-009a topic receiving breq in power-down mode 1. can breq be received in sleep mode? 2. can breq be received in hardware/software standby mode? 1. yes 2. since both the hardware standby mode and software standby mode bring on-chip peripheral modules to a halt (including the clock), breq cannot be received. technical questions and answers 11 classification?8/300h software registers o bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product h8/300h q&a no. qa300h-010a topic maximum wait time after breq input why does it take so long between breq input and back output? because the breq request is held in the following cases: 1. when dmac (dma controller) data is being transferred in burst mode or block transfer mode. 2. when waits are inserted during accesses of external addresses. example: when an instruction with a word-size operand is executed with an 8-bit bus in pin wait mode 1: 1 bus cycle (3 states + inserted wait states + wait states inserted by pin) 2. technical questions and answers 12 classification?8/300h software registers bus controller o interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title see figure 18.17, interrupt input timing, in the following manuals: h8/3002 hardware manual h8/3003 hardware manual see figure 20.17, interrupt input timing, in the following manual: h8/3042 hardware manual question references answer product h8/300h q&a no. qa300h-011a topic interrupt sampling when are external interrupts (nmi, irqn) sampled? sampling occurs at every fall of the system clock f . technical questions and answers 13 classification?8/300h software registers bus controller o interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title see figure 5.2, irq interrupt block diagram, in the following manuals: h8/3002 hardware manual h8/3003 hardware manual h8/3042 series hardware manual question references answer product h8/300h q&a no. qa300h-012a topic holding external interrupts 1. are the irqn interrupt requests held if they are produced when the irqne (irq enable) bit of the ier (irq enable register), which controls external interrupts (irqn), is cleared to 0? 2. are irqn interrupt requests held if they are produced when interrupts are masked with the i and ui bits of the ccr (condition code register)? 1. yes. when the signal specified by the iscr (irq sense control register) drives the irqn pin, the irqnf (irqn flag) of the isr (irq status register) is set to 1. this is not affected by the state of the irqne bit. when the irqne bit is set to 1 while the irqnf is set to 1, an interrupt is requested. the irqnf bit can be cleared with software. 2. yes. as in the above case, irqnf is not affected by the state of the i and ui bits. when the irqne and irqnf bits are set to 1 and the interrupt mask is cleared, the interrupt is accepted. technical questions and answers 14 classification?8/300h software registers bus controller o interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product h8/300h q&a no. qa300h-013a topic receiving nmis during nmi processing if the nmi has the highest priority and is always accepted, will another nmi be accepted if it is generated while the nmi interrupt processing routine is running? if another nmi is generated while an nmi interrupt processing routine is running, that interrupt request is accepted superimposed over the first. technical questions and answers 15 classification?8/300h software registers bus controller o interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product h8/300h q&a no. qa300h-014a topic edge rise and fall times for interrupt pins when an edge trigger is used for an external interrupt, what are the longest allowed rise and fall times of the edge? make it no more than 2 states. more than this will produce the following effects: 1. interrupts will not be accepted because the edge change is not detected. 2. more than one edge will be detected internally for each change in the external pin signal, so multiple interrupts will be requested. technical questions and answers 16 classification?8/300h software registers bus controller o interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title see section 5.5.1, interrupt generation and disable contention, in the following manuals: h8/3002 hardware manual h8/3003 hardware manual h8/3042 series hardware manual also see section 1.3.2, holding external interrupts (qa300h-012a), in this manual. question references answer product h8/300h q&a no. qa300h-015a topic disable timing for interrupts 1. are interrupts disabled the instant that the peripheral module s interrupt enable bit is cleared to 0? 2. when the interrupt enable bit of the ier (irq enable register) is cleared to 0, are interrupt instantly disabled? 1. interrupts are disabled after the instruction that cleared the interrupt enable bit to 0 finishes executing. when an interrupt request is generated while the zeroing instruction is executing, that interrupt request is accepted after the instruction completes its execution. 2. interrupts are disabled after the instruction that cleared the interrupt enable bit to 0 finishes executing. when an interrupt request is generated while the zeroing instruction is executing, that interrupt request is not accepted after the instruction completes its execution since the request signal is cleared simultaneously with the enable bit. however, since the irqn flag is held, the next time the interrupt enable bit is set to 1, that interrupt is accepted. technical questions and answers 17 classification?8/300h software registers bus controller o interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title see section 4.2.3, interrupts after a reset, in the following manuals: h8/3002 hardware manual h8/3003 hardware manual h8/3042 series hardware manual question references answer product h8/300h q&a no. qa300h-016a topic exception processing after a reset are interrupts ever generated immediately following resets? no. immediately after a reset, all interrupts, including nmis, are disabled. however, when the first instruction of a program is executed, nmis are accepted. technical questions and answers 18 classification?8/300h software registers bus controller o interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question answer product h8/300h q&a no. qa300h-017a-1 topic using the interrupt controller how should the two interrupt priority levels be used to make effective use of the interrupt controller? by rewriting the values set in ipra and iprb (interrupt priority registers a and b) for every interrupt processing routine, the interrupt priority can be changed at any time. ipra and iprb are 1-word registers, so they are easy to manipulate. a sample program is shown in figure 1.4. see the procedures after the figure for a more concrete example on use. figure 1.4 sample program saves content of r0 saves ipra value sets the new ipra value to new clears the ui bit reverts to the saved ipra value reverts to the saved r0 value r0 r0 @ipra, r0 #new, r0 r0, @ipra r0, @ipra #h'bf, ccr r0 r0 push push mov.w mov.w mov.w mov.w andc pop pop rte . . . . . . technical questions and answers references 19 answer product h8/300h q&a no. qa300h-017a-2 topic using the interrupt controller 1. procedure for setting interrupt priority: a. set the ue (user bit enable) bit of the syscr (system control register) to 0, the i bit (interrupt mask) of the ccr (condition code register) to 1, and the ccr s ui (user bit/interrupt mask) bit to 0. in this state, only nmis and priority 1 interrupt sources are accepted. b. set the interrupt priorities for each interrupt source on the user end. c. perform the following processing during the interrupt processing routines. following the interrupt priorities set by the user, interrupts of priorities lower than the interrupt in question are masked by writing a 0 to the appropriate bits in ipra and iprb. 2. figure 1.5 shows the processing procedures when the interrupt priorities set by the user are as shown in table 1.4. table 1.4 interrupt priorities interrupt source user-set priorities initial ipra, iprb settings timer 1 5 highest 1 timer 2 4 1 sci 1 3 1 timer 3 2 1 timer 4 1 1 sci 2 0 lowest 1 figure 1.5 processing procedures sci1 interrupt (priority 3) =: ? : _: state processing processing unique to h8/300h timer 2 interrupt (priority 4) ?ui ? 1 (masks interrupts) ?timer 2 interrupt request flag ? 0 ?masks priority 3-0 interrupts; sci1, sci2 of ipra and iprb and interrupts of timers 3 and 4 ? 0 ?ui ? 0 (interrupts enabled for priority 4 or higher) ?ui ? 1 (masks interrupts other than nmi) ?masks priority 2? interrupts (enables priority 3 interrupts); sci2 of ipra and iprb and interrupts of timers 3 and 4 ? 0 (sci1 interrupt ? 1) ?rte ?ui ? 1 (masks interrupts other than nmi) ?enables priority 2? interrupts; sci2 of ipra and iprb and interrupts of timers 3 and 4 ? 1 ?rte main routine ue = 0 i = 1 ui = 0 ?ui ? 0 (interrupts enabled for priority 3 or higher) ?i ? 1, ui ? 1 (masks interrupts other than nmi) ?sci1 interrupt request flag ? 0 ?masks priority 2-0 interrupts; sci2 of ipra and iprb and interrupts of timers 3 and 4 ? 0 ?ui ? 0 (interrupts enabled for priority 3 or higher) ui = 0 technical questions and answers 20 classification?8/300h software registers bus controller o interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title see section 4.2.3, interrupts after a reset, in the following manuals: h8/3002 hardware manual h8/3003 hardware manual h8/3042 series hardware manual question references answer product h8/300h q&a no. qa300h-018a topic receiving an external irq1 after returning from hardware standby mode in the hardware standby mode, i set the irq1 pin to low and then left the hardware standby mode. will interrupts be accepted after returning while the irq1 pin remains low? interrupts will not be accepted immediately after returning. a reset clears hardware standby mode. this initializes the ier (irq enable register) and irq1 becomes disabled (the irq1e (irq1 enable) bit of the ier = 0). thereafter, if the irq1e bit of the ier is set to 1 and the i and ui bits of the ccr enable interrupts, interrupts will be accepted. technical questions and answers 21 classification?8/300h software registers bus controller o interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title see table 5.3, interrupt factors, vector addresses, and interrupt priority ranking (1) , in the following manuals: h8/3002 hardware manual h8/3003 hardware manual h8/3042 series hardware manual question references answer product h8/300h q&a no. qa300h-019a topic interrupt priority within groups 1. when external interrupts occur simultaneously within groups with the same priority (for example, irq4?rq7) which has priority? 2. when an irq4 interrupt occurs during an irq7 interrupt processing routine, what happens? (does irq4 wait or does irq4 processing take priority?) 1. a priority is set within the irq4?rq7 interrupt group of irq4 > irq5 > irq6 > irq7. 2. the irq7 is accepted first. after it is accepted, irq4?rq7 are all masked. when the i (interrupt mask) and ui (interrupt mask) bits of the ccr (condition code register) are enabled during the irq7 processing routine, irq4?rq7 can be accepted. when not enabled in the irq7 processing routine, the irq4 is accepted after returning from the irq7 processing routine. technical questions and answers 22 classification?8/300h software registers bus controller o interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product h8/300h q&a no. qa300h-020a topic interrupts when the bus is released are interrupts that occur when the bus is released held? they are. after the bus release ends, they are accepted after the execution of one instruction. this is the same regardless of whether they are sensed by edge or level. technical questions and answers 23 classification?8/300h software registers bus controller interrupts o resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product h8/300h q&a no. qa300h-021a topic nmi sampling timing and receiving after reset after reset, when does sampling of the nmi signal begin? sampling of the nmi signal begins simultaneously with the fall of the system clock in which the reset clear was sampled. the nmi is not accepted, however, until after the execution of the first instruction after the reset is cleared (see figure 1.6) figure 1.6 nmi sampling timing and receiving after reset f res t ress t resw t ress reset clear sampling nmi not sampled nmi sampled technical questions and answers 24 classification?8/300h software registers bus controller interrupts o resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title see section 4.2.3, interrupts after a reset, in the following manuals: h8/3002 hardware manual h8/3003 hardware manual h8/3042 series hardware manual question references answer product h8/300h q&a no. qa300h-022a topic initializing sp after reset why does the sp (stack pointer) have to be initialized immediately after a reset? if an interrupt is accepted before the sp is initialized, the save address when the pc (program counter) is saved by the interrupt exception processing becomes undefined. the pc could be written to a blank address, to the i/o registers and so on, which makes it impossible to read them correctly on return. this can cause run-away operation. to avoid this, initialize the sp immediately after a reset. technical questions and answers 25 classification?8/300h software registers bus controller interrupts o resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title see section 3.1.1, types of operating mode selection, in the following manuals: h8/3002 hardware manual h8/3003 hardware manual h8/3042 series hardware manual question references answer product h8/300h q&a no. qa300h-023a topic pin state during power-on reset what pin states do i need to pay attention to during power-on resets? during a power-on reset, set the device to an operating mode that uses the mode pins (md0?d2) and keep the stby pin high. also remember that the f output data is undefined until oscillation settles. technical questions and answers 26 classification?8/300h software registers bus controller interrupts o resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product h8/300h q&a no. qa300h-024a topic reso pin output from res pin input what is the reso pin state for reset state ( res = low)? the reso pin is high impedance for reset state ( res = low). it does not go to reset output ( reso = low). technical questions and answers 27 classification?8/300h software registers bus controller interrupts o resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product h8/300h q&a no. qa300h-025a topic connecting res and reso pins is there any problem with taking reso pin low output and inputting it directly to the res pin? yes. when a wdt (watchdog timer) overflow causes reso output to be input directly to the res pin, a reset caused by res pin input is triggered at that moment and everything internal to the lsi, including the wdt, is initialized. this forcibly disables the reso output as well, meaning that the res input spec t resw ( res pin pulse width) minimum of 10 t cyc cannot be satisfied and the operation of the h8/300h cpu after that point cannot be guaranteed. a buffer thus needs to be inserted to ensure that the reso output does not find its way to the res pin. (see figure 1.7.) figure 1.7 connecting r r r r e e e e s s s s and r r r r e e e e s s s s o o o o pins res h8/300h peripheral lsi external reset res reso technical questions and answers 28 classification?8/300h software registers bus controller interrupts o resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title see section 4.2.2, reset sequence, in the following manuals: h8/3002 hardware manual h8/3003 hardware manual h8/3042 series hardware manual question references answer product h8/300h q&a no. qa300h-026a topic cautions for reset input are there any cautions for reset input? when the res pin is made low, a reset begins, but to be sure that a reset is performed, it must be low for at least 20 ms when the power is turned on and at least 10 system clock cycles when operating. when it goes high thereafter, reset exception processing begins. if these conditions are not satisfied, operation thereafter cannot be guaranteed. technical questions and answers 29 classification?8/300h software registers bus controller interrupts resets o power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title see section 17.5.1, transition to hardware standby mode, in the following manuals: h8/3002 hardware manual h8/3003 hardware manual see section 19.5.1, transition to hardware standby mode, in the following manual: h8/3042 series hardware manual question references answer product h8/300h q&a no. qa300h-027a topic executing instructions when switching to hardware standby mode what happens to executing instructions when the stby pin goes low and the hardware standby mode is entered? the executing instruction halts without waiting to finish and its operation cannot be guaranteed. to preserve the contents of ram, clear the rame (ram enable) bit of the syscr (system control register) to 0. technical questions and answers 30 classification?8/300h software registers bus controller interrupts resets o power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product h8/300h q&a no. qa300h-028a topic mode pins during hardware standby mode what happens when the mode pins (md2?d0) are changed in hardware standby mode? the result is abnormal hardware standby mode operation. do not change the mode pins while in hardware standby mode. when the mode is changed to prom mode, for example, the power consumption goes up. technical questions and answers 31 classification?8/300h software registers bus controller interrupts resets o power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title see appendix e, hardware standby mode transition (return timing), in the following manuals: h8/3002 hardware manual h8/3003 hardware manual h8/3042 series hardware manual question references answer product h8/300h q&a no. qa300h-029a topic returning from hardware standby mode i know that the res pin has to be kept low and the stby pin changed to high to return from hardware standby mode, but how long before the stby pin is changed to high does the res pin have to be low? to return from hardware standby mode, the res pin has to be low for 100 ns before the stby pin is changed to high. (see figure 1.8.) figure 1.8 standby release timing stby res 100 ns t osc technical questions and answers 32 classification?8/300h software registers bus controller interrupts resets o power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question answer product h8/300h q&a no. qa300h-030a topic interrupt sampling and receiving in sleep mode 1. when are external interrupts sampled during sleep mode? 2. how many states after an interrupt is sampled is sleep mode cleared? 1. sampling is the same as during program execution. sampling occurs at every fall of the system clock. 2. sleep mode is cleared 6 states after the interrupt is sampled. (see figure 1.9.) figure 1.9 timing of clearing sleep mode by interrupt 123 4 5678 f address bus data bus (d15?0) interrupt request signal 1: sp-2 2: sp-4 3, 4: interrupt vector address 5, 6: saved pc and saved ccr 7, 8: interrupt processing routine start address (contents of vector address) note: example is an h8/3003 (16-bit bus mode, 2-state access, stack is external memory) sleep mode 6 states technical questions and answers 33 classification?8/300h software registers bus controller interrupts resets o power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question answer product h8/300h q&a no. qa300h-031a topic execution time in software standby mode how many states are needed to transition to the software standby mode using a sleep instruction? the time required to transition to the software standby mode is the time (states) required for the sleep instruction to execute. when the sleep instruction is stated in on-chip memory, it takes 2 states; when the sleep instruction is in external 8-bit 3-state-access space, it takes 6 states. the figure below shows the timing for execution of the sleep instruction. (see figure 1.10.) figure 1.10 sleep instruction timing 12 3 4 sleep instruction execution time sleep mode f internal address bus internal data bus (16 bits) 1: pc 2: pc+2 3: sleep instruction 4: next instruction (not executed) technical questions and answers 34 classification?8/300h software registers bus controller interrupts resets o power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question answer product h8/300h q&a no. qa300h-032a-1 topic operation when an interrupt is requested during execution or while fetching a sleep instruction how does the h8/300h cpu operate when an interrupt comes in during a sleep instruction fetch or while a sleep instruction is executing? operation varies, depending on the time the interrupt request occurs, as shown below: a. during sleep instruction fetch: the interrupt exception processing starts after the previous instruction finishes executing. the saved pc becomes the address of the sleep instruction. after returning from the interrupt service routine, the sleep instruction executes. b. during sleep instruction execution (case 1): interrupt exception processing starts without going through the sleep state. the saved pc becomes the address of the instruction after the sleep instruction. after returning from the interrupt service routine, the instruction after the sleep instruction executes. c. during sleep instruction execution (case 2): the sleep mode is canceled 6 states later and the interrupt service routine starts. (see figure 1.11.) technical questions and answers references 35 answer product h8/300h q&a no. qa300h-032a-2 topic operation when an interrupt is requested during execution or while fetching a sleep instruction figure 1.11 timing when an interrupt request occurs during sleep instruction fetch or execution 12 3 (a) (b) (c) 4 nop instruction sleep instruction sleep mode f internal address bus internal data bus (16 bits) interrupt request signal 1: sp 2: sp + 2 3: sleep instruction 4: next instruction note: during h8/3003 (mode 2, 2-state access) technical questions and answers 36 classification?8/300h software registers bus controller interrupts resets power-down mode o instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product h8/300h q&a no. qa300h-033a topic support for the daa (das) instruction with the inc (dec) instruction actual operation is determined by the flag state. 1. the daa instruction can be used with an add instruction (add), but how about executing it after an inc instruction executes? 2. the das instruction can be used with a subtract instruction (sub), but how about executing it after an dec instruction executes? 1. execution of a daa instruction after execution of an inc instruction is not supported, since the c and h flags do not reflect the results of the operation after inc instruction execution. to increment decimal data, execute a daa instruction after adding 1 with the add instruction (add.b #1, rd). 2. execution of a das instruction after execution of an dec instruction is not supported, since the c and h flags do not reflect the results of the operation after dec instruction execution. to decrement decimal data, execute a das instruction after adding ? with the add instruction (add .b #?, rd) and inverting the c and h flags (xorc #a0, ccr). technical questions and answers 37 classification?8/300h software registers bus controller interrupts resets power-down mode o instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product h8/300h q&a no. qa300h-034a topic bra and brn instructions 1. what is the difference between bra (bt) and jmp? also, what does it mean for the condition to be "true"? 2. what does it mean for the brn (bf) condition to be "false"? 1. the bra instruction can be used just like the jmp instruction, but differs in the following points: it can only branch in the range +127 bytes to ?28 bytes for d:8 and +32767 bytes to ?2768 bytes for d:16. if the relative values of objects do not change, the program can be relocated. execution states and instruction size are different. assembler format is different. a condition of true means that since this instruction always branches, the branch condition is always true. 2. a condition of false means that since this instruction never branches, the branch condition is always false. technical questions and answers 38 classification?8/300h software registers bus controller interrupts resets power-down mode o instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product h8/300h q&a no. qa300h-035a topic brn instruction like brn, bra (bt) is convenient to use during debugging. what kind of instruction is brn (bf)? brn is a convenient instruction that replaces conditional branch instructions during debugging. it operates the same as the nop instruction, but its size and execution time differ as described in table 1.5. table 1.5 the brn instruction instruction instruction size (bytes) instruction execution time (states) brn d:8 2 4* d:16 4 6* nop 2 2* note: for a 16-bit bus/2-state access space or an instruction fetch from the on- chip rom. technical questions and answers 39 classification?8/300h software registers bus controller interrupts resets power-down mode o instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product h8/300h q&a no. qa300h-036a topic the subx instruction why does the subx instruction (subtraction with carry) preserve the z flag when the result of execution is 0? the subx instruction is used to divide a subtraction operation into multiple subtractions. after the subx instruction is executed, the z flag reflects the result of all of these operations (see figure 1.12.). it does not reflect the results of each individual subx instruction. figure 1.12 z flag when the subx instruction results in a 0, the z flag thus holds the result of the previous operation. sub rml, rnl reflected in z flag subx rmh, rnh technical questions and answers 40 classification?8/300h software registers bus controller interrupts resets power-down mode o instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product h8/300h q&a no. qa300h-037a topic odd address values during stc instruction execution what is the odd address value when an stc instruction is executed and the ccr stored in an (register indirect) even address? undefined. technical questions and answers 41 classification?8/300h software registers bus controller interrupts resets power-down mode o instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title see section 2.2.28 (items 1 and 2), eepmov, in the following manual: h8/300h series programming manual question references answer product h8/300h q&a no. qa300h-038a topic interrupts and dma transfer requests while the eepmov instruction is executing 1. when an interrupt occurs during the execution of an eepmov instruction, what happens to that interrupt request? 2. what happens when a dma transfer request occurs during the execution of an eepmov instruction? 1. when an interrupt occurs during the execution of an eepmov.b instruction, the interrupt is held and accepted when the instruction finishes executing. it is handled the same as when an interrupt occurs during ordinary instruction execution. however, nmis that occur during eepmov.w execution are accepted after transfer of the byte in transfer is completed. for interrupts other than nmis, operation is the same as for eepmov.b. 2. the dma transfer is executed between the read cycle and write cycle of the eepmov instruction. technical questions and answers 42 classification?8/300h software registers bus controller interrupts resets power-down mode o instructions miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title see section 2.2.28 (1), (2) eepmov h8/300h series programming manual question references answer product h8/300h q&a no. qa300h-039a topic the difference between eepmov.b and eepmov.w what is the difference between eepmov.b and eepmov.w? the transfer data size of both the eepmov.b and eepmov.w instructions is byte, but there are some differences, as described below. size of register that counts the transfer bytes: eepmov.b: byte (maximum number of transfer bytes is 255). eepmov.w: word (maximum number of transfer bytes is 65535). enable/disable of interrupt acceptance: eepmov.b: accepted after instruction executes (all held). eepmov.w: nmi alone is accepted after transfer of byte in transfer is completed (all others held). technical questions and answers 43 classification?8/300h software registers bus controller interrupts resets power-down mode instructions o miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title see section 2.4.4 inicial cpu resistor, section 2.5.2 memory data formats, in the following manuals: h8/3002 hardware manual h8/3003 hardware manual h8/3042 series hardware manual question references answer product h8/300h q&a no. qa300h-040a topic cautions on stack operation are there any particular cautions about stack operation to be aware of? on the h8/300h, the stack area is always accessed by word or longword. when the stack pointer is set to an odd number, malfunctions can result. use the push or pop instructions to stack. the initial value of sp (stack pointer) is undefined. it is initialized by the user. technical questions and answers 44 classification?8/300h software registers bus controller interrupts resets power-down mode instructions o miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product h8/300h q&a no. qa300h-041a topic on-chip peripheral lsi access when the bus is released can external devices (bus master) access internal registers of the h8/300h when the h8/300h cpu has released the bus to an external device? no. internal registers cannot be accessed from external devices. technical questions and answers 45 classification?8/300h software registers bus controller interrupts resets power-down mode instructions o miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product h8/300h q&a no. qa300h-042a topic areas that can be used as rom by the vector table items reserved by the system are used by development tools. addresses reserved by the system and reserve addresses are listed in the manual. branch address areas of "memory indirect" addressing can use addresses other than those reserved by the system or those of used by the vector table. 1. can the empty areas of the vector table (reserved by system or reserve) be used as rom? 2. can the empty areas of the i/o registers be used as rom? 1. the vector numbers reserved by the system (4?) on the vector table cannot be used. reserve addresses, however, can be used as rom. unused interrupt vector addresses on the vector table can also be used. 2. the empty areas of the i/o registers cannot be used. technical questions and answers 46 classification?8/300h software registers bus controller interrupts resets power-down mode instructions o miscellaneous dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product h8/300h q&a no. qa300h-043a topic pin state during the oscillation settling time what are the pin states during oscillation settling time after the software standby mode is cleared? the same as in the software standby mode. technical questions and answers 47 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous o dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question answer product common q&a no. qa300h-101-1 topic receiving dmac startup requests when a dma controller startup request occurs: 1. when is the request forced to wait? 2. is the request accepted under the following conditions? during eepmov execution during read-modify-write instruction execution during dmac cycle steal transfers. 1. the bus arbiter priority order is: external bus master > refresh controller > dmac > cpu. this means that dma requests are not accepted when an external bus master or refresh controller with a priority higher than the dmac has the bus. since the dmac channels have the priorities (for h8/3003) shown in table 2.1, the request waits when a higher priority channel is transferring. table 2.1 dmac channel priority short address mode full address mode priority channel 0 a channel 0 highest channel 0 b channel 1 a channel 1 channel 1 b channel 2 a channel 2 channel 2 b channel 3 a channel 3 lowest channel 3 b technical questions and answers references section 2 on-chip peripherals 48 answer product common q&a no. qa300h-101-2 topic receiving dmac startup requests 2. during eepmov execution, requests are accepted between the read cycle and the write cycle. during read-modify-write instruction execution, requests are accepted between the read cycle, instruction fetch, and the write cycle. during cycle steal transfers, requests are accepted if the channel of the transfer request is higher in priority than the current channel. technical questions and answers references 1. bset, bclr, bnot, bst and bist are read-modify-write instructions. 2. when the wait is longer than those described above, wait states may have been inserted by a cpu bus cycle that has a dreq request. (see figure 2.1.) figure 2.1 wait state insertion t1 t2 tw t3 t1 t2 tw t3 cpu cycle cpu cycle dma cycle dreq request requires 7 states in the case shown 49 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous o dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question answer product common q&a no. qa300h-102 topic addresses during dma transfers doesn t the cpu cause problems in dmac operation if it reads the mar (memory address register) during dma transfers? reading the mar does not have any affect on dma operation. however, when longword data is read, a dma cycle can enter in between reading of the top 16-bits of data and the bottom 16-bits of data, as described in the manual. as a result, the value read may differ from the actual value. the timing at which the mar is updated is shown in figure 2.2. figure 2.2 mar update timing td t1 t2 t1 t2 123 1' dma cycle transfer source 1. mar updated at transfer source. 2. counter updated. 3. mar updated at transfer destination note: mar also updated at transfer source at 1' (during burst transfers and in the block transfer mode). transfer destination technical questions and answers references there should be no mistake in the value read so long as the bottom 16-bit (marh, marl) value is read with the mov.w instruction. 50 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous o dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-103 topic tend signal output timing 1 is the tend signal output at every byte/word transfer? the tend signal is output when the startup source is an external request (using the dreq pin). in operating modes other than block transfer mode, the tend signal is driven low during the final transfer write cycle. for block transfers, it is low during the write cycle just before the end of a 1 block transfer. it is not output at every byte/word. (see figure 2.3.) figure 2.3 t t t t e e e e n n n n d d d d output final dma cycle cpu cycle td t1 t2 t1 t2 tend hwr, lwr rd address bus f technical questions and answers 51 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous o dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-104 topic tend signal output timing 2 at what timing is the tend signal output? the tend signal is output in the write cycle when the etcr (transfer count register) becomes h'00. figure 2.4 illustrates the timing. figure 2.4 t t t t e e e e n n n n d d d d output timing final dma cycle cpu cycle td t1 h'01 h'00 t2 t1 t2 tend hwr, lwr rd address bus etcr f technical questions and answers 52 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous o dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-105 topic the relationship between the dmac s dte and dtie bits when the dtie (data transfer interrupt enable) bit is 1 and the dte (data transfer enable) bit is then cleared to 0, the manual says that an interrupt is requested of the cpu. 1. will dma transfer end interrupts occur continuously, as shown in figure 2.5? 2. if so, what can be done to keep interrupts from occurring? figure 2.5 continuous interrupts from dte and dtie dte = 0, dtie = 1 dma interrupt processing rte holds the values dte = 0, dtie = 1 1. yes, interrupts will occur continuously. 2. if dte = 0 and dtie = 1 (enabling interrupts), interrupts will always be produced. to prevent this, set dte to 1 (the bset instruction can be used), or clear the dtie bit to 0 (the bclr instruction can be used). technical questions and answers 53 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous o dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question answer product common q&a no. qa300h-106 topic dmac startup when the dmac is started up with an itu compare match interrupt, what happens if the i (interrupt mask) and ui (user bit/interrupt mask) of the ccr (condition code register) are masked? interrupts selected as dmac startup sources are not affected by the cpu s interrupt mask bits (i and ui bits). (see figure 2.6.) figure 2.6 dmac startup cpu ccr dte dmac ui ue syscr i priority determin- ation circuit peripheral module flag for compare match or the like interrupt enable bit technical questions and answers when an interrupt is disabled with an interrupt enable bit in a module, interrupts will not occur for either the dmac startup request or the cpu. references 54 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous o dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-107 topic the dmac and timer interrupts when the dmac startup source has compare-matched the itu, is an interrupt produced to the cpu of the itu? interrupt requests selected as startup sources startup the dmac when the dte (data transfer enable) bit of the dmac s dtcr (data transfer control register) is set to 1, and no interrupt is generated to the cpu. when the dte bit is 0, no startup request is generated and an interrupt goes to the cpu. an interrupt that is used as a startup source cannot simultaneously generate an interrupt to the cpu. technical questions and answers 55 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous o dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title see section 8.6, cautions on use, in the following manuals: h8/3002 hardware manual h8/3003 hardware manual h8/3042 series hardware manual question references answer product common q&a no. qa300h-108 topic operation after a dmac end interrupt is generated 1 when the transfer count register becomes h'0000 while the dmac is in use and an end interrupt is generated: 1. when is the next transfer request accepted? 2. are transfer requests generated before the dma transfer starts ignored? 1. the next transfer request is accepted when the dte (data transfer enable) bit is set to 1 by software. when the transfer count register reaches h'0000 and a transfer end interrupt is generated, the dte bit of the dtcr (data transfer control register) is cleared and data transfer is disabled. to do another transfer, set the transfer count register during the end interrupt routine and then set the dte bit to 1. 2. when the startup request is an internal interrupt, a cpu interrupt is requested when the dte bit is 0. for more information, see the hardware manual. when the startup request is an external request, it is ignored if it is an edge. technical questions and answers 56 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous o dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-109 topic operation after a dmac end interrupt is generated 2 when the transfer count register becomes h'0000 while the dmac is in use and the transfer ends, when is the transfer end interrupt generated? after the transfer ends, an interrupt request is generated and the bus is released. when the cpu captures the bus, the transfer end interrupt is performed after the executing instruction ends. (see figure 2.7.) figure 2.7 timing at dmac end interrupt f transfer end interrupt signal cpu cycle final dma transfer cycle cpu cycle exception processing started by dmac transfer end interrupt technical questions and answers 57 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous o dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-110 topic dma transfers started up by serial transfers can more than 256 transfers be done between memory and i/os when sci and dmac are used together to send and receive? when the dmac is started up by the sci, i/o mode should be used. the maximum number of transfers allowed will then be 65,536. to transfer more data than this, data must be stored in memory and the transfer counter reset with a transfer end interrupt. technical questions and answers 58 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous o dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-111 topic time until dmac startup by the dreq pin why is 4 states the minimum time to startup the dmac from the dreq pin? the delay time from the dreq pin to the internal dmac module is 2 states. the bus arbiter internal processing time is also 2 states. this means a minimum of 4 states (the sum of these figures) is required. technical questions and answers 59 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous o dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question answer product common q&a no. qa300h-112 topic reverse operation in the dma repeat mode what do i do to pause a dma transfer that uses repeat mode and then start it up in the opposite direction? the flowchart in figure 2.8 illustrates the process. figure 2.8 reverse operation in the dma repeat mode disable internal interrupts that cause start-ups forward byte transfer (dtid = 0) dmac halted reversed byte transfer (dtid = 1) i: number of transfer cycles. i = etcrl?tcrh. dte = 0 i 2 * enable internal interrupts that cause start-ups mar = mar ?2 etcrh = i ?1 true false mar = mar + (etcrl + i ?2) etcrh = etcrl + i ?1 dte = 1 technical questions and answers 60 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous o dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title see section 9, i/o ports, in the following manual: h8/3003 hardware manual question references answer product common q&a no. qa300h-113 topic use of dual-function pins when the dmac is used under the following conditions, can the tend / cs dual-function pin be used as a cs output? conditions: full-address transfer mode, external request (low level input from dreq pin) for the startup source. it cannot be used as a cs output. when external request is selected as the startup source, the tend / cs dual-function pin concerned becomes a tend output pin. for more information, see the i/o port section in the hardware manual. technical questions and answers 61 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous o dma controller itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-114 topic i/o ports and the dreq pin 1. how should the dte (data transfer enable) bit of the dtcr (data transfer control register) be set to use pins that are used both as dreq pins and i/o ports as i/o ports? 2. how should dual-function pins be set for use as dreq pins? 1. they can be used as i/o ports without regard to the dte bit. 2. to use dual-function pins as dreq pins, clear the ddr (data direction register) of affected ports to 0. when the ddr is set to 1, port output is detected as dreq input. technical questions and answers 62 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller o itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-115 topic pwm mode and interrupts to clear the imfb flag, use the bclr instruction. when the itu is used in the pwm mode and interrupts are enabled, is it necessary to clear the imfb (input capture/compare match flag b) of the tsr (timer status register) to 0 within the interrupt processing routine or is the imfb automatically cleared when an imib interrupt is generated? the imfb flag must be cleared to 0 within the interrupt processing routine. the timing when the flag is cleared by the program is shown in figure 2.9. figure 2.9 imfb flag t1 t2 tsr address flag cleared address imf t3 f technical questions and answers 63 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller o itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-116 topic clearing the counters how do i clear the itu counter using software? clear the tcnt (timer counter) by writing h'0000 to it. the counter value is not cleared by rewriting the tstr (timer start register). technical questions and answers 64 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller o itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-117 topic pulse output from the itu how do i get a specific number of pulses output (say, 10) and then stop the pulse output? 1. when 1 dmac channel can be used: pulses are output in the itu s pwm mode. in this case, the dmac is started up by an itu compare match . set dma transfers for 10 and generate a transfer end interrupt to stop the itu. this dma transfer is aimed at starting up 10 times; set the data transfer so that it does not affect cpu operation (transfer data, transfer source address, transfer destination address). 2. when other timers can be used: output pulses are input to the tclk pin (clock input pin) and events counted by another timer (x). when the timer (x) compare register reaches a count of 10, a compare match interrupt is generated and the itu stops. on the h8/300h, tioca0/tclkc and tiocb0/tclkd are dual- function pins. for this reason, no extra wiring needs to be added on the board to output pulses from channel 0 and use tclkc and tclkd as input pins. 3. when using software: generate compare match interrupts each time and count with the interrupt processing routine. technical questions and answers 65 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller o itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-118 topic itu cascade connections can cascade connections be used with the itu? the pa2 and pa3 pins of port a are dual function pins for outputs tioca0 and tiocb0 of the itu s channel 0 and clock inputs tclkc and tclkd. this enables direct itu cascade connections without external wiring. the count timing for the itu in the host is shown in figure 2.10. figure 2.10 itu count timing when there is no wiring from tioca0/tclkc or tiocb0/tclkd to off the chip and the load is light, tclkc and tclkd sample the compare match output of tioca0 and tiocb0 at the rise of the next f . sampling tioca0/tclkc tiocb0/tclkd f (system clock) technical questions and answers 66 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller o itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-119 topic setting the itu s pwm output when the itu is used in pwm mode, how should the tior (timer i/o control register) be set? the tior setting does not affect pwm output. when the pwm mode is set with the pwm bit of the tmdrs (timer mode registers) located in each of the channels of the itu, gra/grb are used as output compare registers for output setting, regardless of the contents of the tior. technical questions and answers 67 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller o itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references product common q&a no. qa300h-120-1 topic itu output and port output when the itu is set to toggle output on a grb (output capture/input compare dual-function register b) compare match to get the output shown in figure 2.11, what kind of value is output when changing from port output to itu output? figure 2.11 itu output and port output (q) (tcnt value) grb tiocb output, port output set for toggle output upon compare match in the tior (timer i/o control register) set for port output with output upon compare match in the tior (timer i/o control register) disabled set for toggle output upon compare match in the tior (timer i/o control register) itu output high output or low output? port output itu output (time) technical questions and answers 68 answer product common q&a no. qa300h-120-2 topic itu output and port output 1. when port output is changed to itu output, the value from before the change is output. 2. when a compare match signal is generated at the point when the port output is to be changed to itu output, the value changes. (see figure 2.12.) figure 2.12 itu output and port output (a) i/o port output itu output itu output port output set to low by program set to itu toggle output again in program case 1 tiocb output, port output high output before set for port output output becomes high at itu toggle output i/o port output itu output low level output, since compare match signal is generated before setting to itu output itu output port output set to low by program set to itu toggle output again by program case 2 tiocb output, port output compare match signal output becomes high at itu toggle output technical questions and answers references 1. when the itu was started after a reset, the tiocn output is low until the first compare match occurs. 2. when set to input capture and output is disabled, the output level changes when an input capture occurs. 69 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller o itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question answer product common q&a no. qa300h-121-1 topic itu settings please explain in detail the pulse width, cycle settings and register settings for itu pulse output as well as the relationship to the internal clock. when outputting pulses in the pwm mode, the duty can be found from the following equation. duty = n + 1 / n + 1 where gra = n (set the counter value corresponding to the low width ?1), and grb = n (set the counter value corresponding to the cycle ?1) example: when the operating frequency is 10 mhz, the internal clock for the count is f /2 and grb = 9, so to get a duty of 50% (with an n of 9): (n + 1)/(9 + 1) = 0.5 gra must be set to 4. the exact timing is shown in figures 2.13 to 2.16. technical questions and answers references 70 answer product common q&a no. qa300h-121-2 topic itu settings figure 2.13 itu settings (1) figure 2.14 itu settings (2) figure 2.15 itu settings (3) h'0000 internal clock ( f /4) tcnt tioca f h'0001 h'0000 h'0000 1.5 t cyc 1.5 t cyc internal clock ( f /4) tcnt tioca f n + 1 n + 1 n n n ?1 n ?1 compare match occurs 0.5 t cyc internal clock ( f /4) tcnt tioca f h'0000 n n n ?1 n ?1 compare match occurs 0.5 t cyc technical questions and answers 71 answer product common q&a no. qa300h-121-3 topic itu settings figure 2.16 itu settings (4) tcnt value grb (n) gra (n) tioca output figure 2.13 figure 2.14 n n time figure 2.15 technical questions and answers 72 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller o itu watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-122 topic independent operation of tcnt4 using reset-synchronized pwm mode the manual states that "tcnt4 runs independently" when reset- synchronized pwm mode is used. do this mean it can be used for other purposes? reset-synchronized pwm mode uses channel 3 and 4 together, but the only counters and registers it uses are tcnt3, gra3, gra4, grb3 and grb4. this allows tcnt4 to be used independently. one way to use it might be to run it as an interval timer using counter overflows. technical questions and answers 73 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu o watchdog timer sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-123 topic halting the wdt s system clock when the system clock is halted, does the wdt (watchdog timer) detect abnormalities? when the system clock of the entire lsi is halted, the wdt count stops as well, so it cannot detect abnormalities. technical questions and answers 74 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer o sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-124 topic using the rdr and tdr when the sci is not being used when the sci is not being used: 1. can the rdr (receive data register) be used as a data register? 2. can the tdr (transmit data register)? yes and no. 1. the rdr cannot be used as a data register because it is a read-only register. 2. the tdr can be used as a data register. technical questions and answers 75 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer o sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-125 topic i/o settings of clock pins for the sci when the sci is being used, does the ddr (data direction register) of the port for the sck (serial clock) pin set the i/o specification for that pin? the i/o direction for the sck pin when the sci is being used is specified by the c/ a bit (communications mode) of the smr (serial mode register) and the cke1 and cke0 (clock enable) bits of the scr (serial control register). setting the ddr of the port is not necessary. technical questions and answers 76 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer o sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-126 topic serial i/o pin state after using the dual-function pins that can be used as i/o ports (txd, rxd and sck) as sci pins, i reset them as i/o ports with the scr (serial control register) and smr (serial mode register). what happens to the values of the ddr (data direction register) pins when this happens? sci operation does not affect the contents of the ddr of the i/o port. this means that in the case described above the ddr holds the value it had before being set as an sci pin. technical questions and answers 77 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer o sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-127 topic simultaneous transmission and reception with the sci when the sci is being used, can transmission using the internal clock occur simultaneous with reception on the external clock (or vice versa)? only 1 clock source can be selected as the sci transfer clock. this prevents simultaneous transmission and reception using 2 types of clocks. simultaneous transmission/reception using the same clock is possible. technical questions and answers 78 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer o sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-128 topic rdrf what happens if, when clearing the rdrf (receive data register full) flag of the ssr (serial status register) to 0 during sci reception, it is cleared to 0 directly without first reading a 1? it will not be cleared. when the bclr instruction is used, the ssr is first read in byte units, then the bit that corresponds to the rdrf flag is cleared to 0 and a write occurs, again in byte units. while the rdrf flag is set to 1 (rxi interrupt processing routine), the bclr instruction thus cannot clear the rdrf flag. technical questions and answers 79 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer o sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question answer product common q&a no. qa300h-129-1 topic setting for asynchronous transmission asynchronous transmission uses the sci. how do i set it to do a transfer by software (i.e., using the data empty interrupt (txi) but not the dmac)? when the tdre = 1, the data empty interrupt is always generated and the tie is set to 1. there are thus 2 methods. 1. setting the first byte with an interrupt processing routine: rn ? 0 (transfer counter) te = 1 (transfer enable) tie = 1 (empty interrupt enable) 2. setting the first byte with the initialization: rn ? 1 (transfer counter) te = 1 (transfer enable) first byte set to tdr tdre cleared (transfer starts, tdre = 1 after tdr ? tsr tie = 1 (empty interrupt enable) in either case, the txi interrupt processing routine is as shown in the figure 2.17. technical questions and answers references 80 answer product common q&a no. qa300h-129-2 topic setting for asynchronous transmission figure 2.17 txi interrupt processing routine rn rn + 1 (empty interrupt generation) (rn)th byte of data is written to tdr; tdre is cleared (tdre is read and cleared) rte rn = 16 no yes tie = 0 (interrupt disabled) technical questions and answers 81 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer o sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question answer product common q&a no. qa300h-130-1 topic how data is transferred to the tdr are there ways, when transferring transfer data located in 16-bit bus space to the sci s transmit data register (tdr, length 8 bits) as shown in figure 2.18, to: 1. transfer using software? 2. use the dmac? figure 2.18 transferring data to the tdr h8/3003 sci data transfer dmac dram transfer data 16-bit data bus 1. 16-bit bus spaces can be accessed in byte units. read transfer data on the dram 1 byte at a time and transfer it to the sci s tdr. to transfer data stored in the transfer buffer, do as shown in figure 2.19. figure 2.19 transfer buffer 10000 10010 note: start address of transfer buffer 10000 stored in er0. technical questions and answers references 82 answer product common q&a no. qa300h-130-2 topic how data is transferred to the tdr loop: mov.b #12,r2l set the number of transfer words waiting for interrupt can be placed in the sleep mode dec.b r2l copy the transfer data (1 byte) to r3l and increment the transfer buffer pointer (er0) by 1 bne loop continue until the transfer counter hits 0 txi interrupt: mov.b @er0+,r3l transfer the transfer data to the sci s tdr mov.b r3l,@tdr decrement transfer counter by 1 bclr #7,@ssr clear tdre to 0 bne loop return to main routine 2. using the dmac: start up the dmac with the sci s txi interrupt and transfer the transfer data on dram 1 byte at a time to the sci s tdr. byte needs to be specified as the size in the dmac. (word size transfers are impossible, since they start up the dmac at every transmission of a byte.) technical questions and answers references the bus controller function can be used to enable word-sized transfers as shown in figure 2.20. for each read cycle (16-bit data), 2 consecutive write cycles of 8-bit data are necessary. figure 2.20 using the bus controller function to enable word-sized transfers h8/300h ram in 16-bit address space dma transfer ram in 8-bit space 83 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer o sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question answer product common q&a no. qa300h-131a-1 topic timing of setting rdrf 1. when data reception ends, the rdrf (receive data register full) flag of the ssr (serial status register) is set to 1. at what point in the asynchronous mode is the rdrf set? 2. when is it set in clock-synchronous mode? 1. the rdrf flag is set after the msb data is received and the data sampling clock falls. (see figure 2.21.) figure 2.21 8-bit data, 1 stop bit 123456789101112 1314151612345678 9 10111213141516 stop d7 basic clock receive data data sampling rdrf note: when sck clock source is the internal clock, 0.5 basic clocks + 2 states. when sck clock source is an external clock, 3-4 states. technical questions and answers references 84 answer product common q&a no. qa300h-131a-2 topic timing of setting rdrf 2. the rdrf flag is set after the msb data is received and synchronization clock rises. (see figure 2.22.) figure 2.22 8-bit data synchronization clock receive data rdrf note: when sck clock source is the internal clock, 1 state. when sck clock source is the external clock, 2-3 states. bit 6 bit 7 technical questions and answers 85 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer o sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question answer product common q&a no. qa300h-132a-1 topic timing of setting tdre 1. when 8-bit data transmission ends, the tdre (transmit data register empty) flag of the ssr (serial status register) is set to 1. at what point in the asynchronous mode is the tdre set? 2. when is it set in clock-synchronous mode? the tdre flag is set at different times when there is transmission data in the tsr (transmit shift register) and when there is not. 1. asynchronous mode. (see figure 2.23.) figure 2.23 transmit data in tsr (asynchronous mode) 123456789101112 1314151612345678 9 10111213141516 basic clock transmit data tdre stop bit start bit when sck clock source is the internal clock, 4 state. when sck clock source is the external clock, 4? state. technical questions and answers references 86 answer product common q&a no. qa300h-132a-2 topic timing of setting tdre the start of transmission according to the setting of the te (transmit enable) bit also follows this timing. (see figure 2.24.) figure 2.24 no transmit data in tsr (asynchronous mode) 2. clock-synchronous mode (see figures 2.25 and 2.26.) figure 2.25 transmit data in tsr (clock-synchronous mode) figure 2.26 no transmit data in tsr (clock-synchronous mode) 9101112131415161234 5678910111213141516 12345678 10 9 11121314 t1 f internal write signal basic clock tdre t2 t3 2.5 states synchronization clock transmit data tdre bit 6 bit 7 when sck clock source is the internal clock, 2 state. when sck clock source is the external clock, 1.5?.5 state. f internal write signal tdre t1 t2 t3 2.5 states tdre set timing technical questions and answers 87 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer o sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-133 topic sci reception errors by returning to the main routine during a receive error interrupt routine without clearing the reception error flags of the ssr (serial status register), is a receive error interrupt generated again? the receive error flag is not automatically cleared. after returning to the main routine (after executing the rte instruction), a receive error interrupt will be generated again. technical questions and answers 88 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer o sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-134 topic operating the sci in external clock mode when the sci is operated in clock-synchronous external clock mode: 1. does the sci start the next transmit operation if, after the completion of 1 byte of data transmission, the external clock is applied to the sck pin before the h8/300h cpu writes to the tdr (transmit data register)? 2. what happens after reception? the results are as follows: 1. transmission does not start. the next transmission will not start until the tdre (transmit data register empty) of the ssr (serial status register) is cleared to 0. 2. reception starts, however, an overrun error will occur unless the rdrf (receive data register full) of the ssr is cleared before the next data is completely received. technical questions and answers 89 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer o sci a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-135 topic system clocks and sck phases is the sck (serial transfer clock) output synchronous to system clock ( f ) rise or fall? the sck signal is output synchronous to system clock ( f ) fall. technical questions and answers 90 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci o a/d converter i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-136 topic changing the a/d mode and channel during a/d conversion before switching the a/d conversion mode or changing the selected channel, check the adf (a/d end flag) in the adcsr (a/d control/status register). 1. how do i switch the a/d conversion mode during a/d conversion? 2. how do i change the selected channel during a/d conversion? 1. switching the a/d conversion mode during a/d conversion will decrease conversion accuracy. we advise against it. 2. changing the selected channel during a/d conversion causes the same problem as switching the conversion mode. again, we advise against it. technical questions and answers 91 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter o i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question answer product common q&a no. qa300h-137 topic using general-purpose ports can instructions that manipulate bits be used on i/o ports when a bit of the port is designated an output port? yes. when a port set as an output port is read by the cpu, the contents of the port data register (dr) are read, regardless of the pin state. when an input port is read, the pin state is read. this means there are no problems in using instructions that manipulate bits. when there are pins in the port that have been designated input ports, however, the dr values of the input ports will become undefined (pin state). (see figure 2.27.) figure 2.27 using general-purpose ports 1 1 1 1 0 0 0 0 output settings input settings read dr values read pin values bit 7 set to 1 by cpu changes with pin status dr contents after instruction bclr #7, @dr is executed 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 ddr contents pin status dr contents read dr 1 1 0 0 0 0 1 0 1 1 0 0 technical questions and answers references the bset, bclr, bnot, bst and bist instructions manipulate bits. 92 classification?8/300h software registers bus controller interrupts resets power-down mode instructions miscellaneous dma controller itu watchdog timer sci a/d converter o i/o ports related manuals manual title other technical documentation document name related microcomputer technical q&a title question references answer product common q&a no. qa300h-138 topic processing ports when not in use how should i process ports that are not in use? 1. clear the ddr (data direction register) of i/o ports to 0 to put them in input state and pull each pin up or down with a resistance of about 10 k w . 2. handle input-only ports the same way. technical questions and answers |
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